ADT7518
 
Rev. A | Page 20 of 40
BIAS
DIODE
INTERNAL
SENSE
TRANSISTOR
V
DD
TO ADC
V
OUT+
V
OUT
I
N ?/SPAN> I
I
BIAS
 
Figure 42. Top Level Structure of Internal Temperature Sensor
 
Table 7. Thermal Voltage Output (0 V to 2 VREF)
O/P Voltage (V)
Default 癈
Max 癈
Sample 癈
0
40
128
0
0.25
26
114
+14
0.5
+12
100
+28
0.75
+3
85
+43
1
+17
71
+57
1.12
+23
65
+63
1.47
+43
45
+83
1.5
+45
43
+85
2
+73
15
+113
2.25
+88
0
+127
2.5
+102
+14
UDB*
2.75
+116
+28
UDB*
3
UDB*
+42
UDB*
3.25
UDB*
+56
UDB*
3.5
UDB*
+70
UDB*
3.75
UDB*
+85
UDB*
4
UDB*
+99
UDB*
4.25
UDB*
+113
UDB*
4.5
UDB*
+127
UDB*
* Upper deadband has been reached. DAC output is not capable of increasing.
See Figure 9. 
Negative temperatures:
( )
128
0
Re
+
=
Temp
V
d
Code
gister
Offset
 
where:
D7 of Offset Register Code is set to 1 for negative temperatures.
Example:
(   )
58h
 
d
88
128
40
d
Re
=
=
+

=
Code
gister
Offset
 
Since a negative temperature has been inserted into the
equation, DB7 (MSB) of the offset register code is set to 1.
Therefore 58h becomes D8h.
58h + DB7(1) = D8h
Positive temperatures:
Offset Register Code (d) = 0 V Temp
 
Example:
Offset Register Code (d) = 10d = 0Ah
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output:
Temp
V
LSB
P
O
DAC
Temp
Bit
-
0
1
/
8
+
 
For example, if the output is 1.5 V, VREF-IN = 2.25 V, 8-bit DAC
has an LSB size = 2.25 V/256 = 8.79 x 10
3
, and 0 V temperature
is at 128癈, then the resultant temperature is
(
)
C
?/DIV>
+
=

+
?/DIV>
?/DIV>

43
128
10
79
.
8
5
.
1
3
 
Figure 43 shows a graph of the DAC output versus temperature
for a VREF-IN = 2.25 V.
TEMPERATURE (?/SPAN>C)
0
0.15
128110 90  70  50  30  10   10    30    50    70    90   110  127
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.80
1.95
2.10
2.25
0V = 128?/SPAN>C
0V = 40?/SPAN>C
0V = 0?/SPAN>C
 
Figure 43. DAC Output vs. Temperature V
REF
-IN = 2.25 V
FUNCTIONAL DESCRIPTIONANALOG INPUTS
Single-Ended Inputs
The ADT7518 offers four single-ended analog input channels.
The analog input range is from 0 V to 2.25 V, or 0 V to VDD. To
maintain the linearity specification, it is recommended that the
maximum VDD value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration 3
register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
reference of 2.25 V. Setting the bit to 1 sets up the ADC
reference to be sourced from VDD.
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